14 #include <rte_compat.h>
50 struct rte_pmd_cnxk_sec_action {
56 uint16_t sa_hi, sa_lo;
63 #define RTE_PMD_CNXK_CTX_MAX_CKEY_LEN 32
64 #define RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN 128
67 #define RTE_PMD_CNXK_AR_WIN_SIZE_MIN 64
68 #define RTE_PMD_CNXK_AR_WIN_SIZE_MAX 4096
69 #define RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 5
72 #define RTE_PMD_CNXK_AR_WINBITS_SZ (RTE_ALIGN_CEIL(RTE_PMD_CNXK_AR_WIN_SIZE_MAX, 64) / 64)
129 uint64_t reserved_0_2 : 3;
130 uint64_t address : 57;
287 uint64_t rsvd10 : 32;
uint64_t ipv4_df_or_ipv6_flw_lbl
union rte_pmd_cnxk_ipsec_inb_sa::@8 w8
uint64_t ar_winbits[RTE_PMD_CNXK_AR_WINBITS_SZ]
union rte_pmd_cnxk_ipsec_inb_sa::@5 w0
__rte_experimental int rte_pmd_cnxk_hw_sa_write(void *device, struct rte_security_session *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len)
struct rte_pmd_cnxk_ipsec_inb_ctx_update_reg ctx
union rte_pmd_cnxk_ipsec_outb_sa::@18 w10
struct rte_pmd_cnxk_ipsec_outb_sa outb
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
union rte_pmd_cnxk_ipsec_outb_sa::@15 w0
union rte_pmd_cnxk_ipsec_inb_sa::@7 w2
uint64_t count_glb_octets
union rte_pmd_cnxk_ipsec_inb_sa::@6 w1
uint64_t tport_l4_incr_csum
union rte_pmd_cnxk_ipsec_outb_iv iv
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
union rte_pmd_cnxk_ipsec_inb_sa::@9 w10
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
#define RTE_PMD_CNXK_AR_WINBITS_SZ
uint64_t udp_ports_verify
uint64_t ipv4_df_src_or_ipv6_flw_lbl_src
union rte_pmd_cnxk_ipsec_outb_sa::@16 w1
struct rte_pmd_cnxk_ipsec_inb_sa inb
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
__rte_experimental void * rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf)
__rte_experimental int rte_pmd_cnxk_hw_sa_read(void *device, struct rte_security_session *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len)
uint64_t count_glb_octets
struct rte_pmd_cnxk_ipsec_outb_ctx_update_reg ctx
rte_pmd_cnxk_sec_action_alg
union rte_pmd_cnxk_ipsec_outb_sa::@17 w2
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr